This invention relates to a level conversion circuit such as one used as the interface between the output of an ECL circuit and the input of a TTL circuit or an N-MOS circuit, for example.
Since the ECL (emitter coupled logic) circuit makes use of a negative power source voltage V.sub.EE, the signal level of the ECL circuit varies between ground potential (GND) and the negative power source voltage V.sub.EE. On the other hand, the TTL (transistor-transistor logic) circuit or the N-MOS (N channel insulated gate field effect transistor) circuit makes use of a positive power source voltage V.sub.CC and hence, the signal level of the TTL circuit or of the N-MOS circuit varies between the positive power source voltage V.sub.CC and ground potential (GND).
As the interface between the output of the first circuit operating on the negative power source voltage V.sub.EE and the input of the second circuit operating on the positive power source voltage V.sub.CC, a signal level conversion circuit is necessary. In an IC.sub.1 encompassed by the two-dot chain line in FIG. 1, a circuit indicated by l.sub.2 is a heretofore known semiconductor integrated circuit, forming a signal level conversion circuit. A first power terminal of the ECL circuit l.sub.1 is connected to the ground potential (GND) and a negative power source voltage V.sub.EE (e.g., -5.2 V) is impressed upon a second power terminal P.sub.2. Accordingly, the signal level of an output signal y obtained from an output terminal P.sub.7 of the ECL circuit l.sub.1 varies between the ground potential (GND) and the negative power source voltage V.sub.EE. A positive power source voltage V.sub.CC (e.g., +5.0 V) is impressed upon a first power terminal P.sub.10 of the TTL circuit l.sub.3 and its second power terminal P.sub.16 is connected to the ground potential (GND). Hence, the signal level of the TTL circuit l.sub.3 varies between the positive power source voltage V.sub.CC and ground potential (GND). The heretofore known level conversion circuit l.sub.2 is disposed between the output terminal P.sub.7 of the ECL circuit l.sub.1 and the input terminal P.sub.15 of the TTL circuit l.sub.3.
The signal level conversion circuit l.sub.2 includes a first input transistor Q.sub.18 having its base connected to the first input terminal P.sub.11, a second input transistor Q.sub.17 having its base connected to the second input terminal P.sub.12, a reference transistor Q.sub.16 the base of which receives a negative second reference voltage V.sub.b2 generated by a reference voltage generation circuit 1 and a current source transistor Q.sub.19 the base of which receives a negative first reference voltage V.sub.b1 generated by the reference voltage generation circuit 1. The reference voltage generation circuit 1 operates on the difference voltage between the negative power source voltage V.sub.EE and the ground potential (GND) and includes transistors Q.sub.9 and Q.sub.10, diodes D.sub.3 -D.sub.6 and resistors R.sub.7, R.sub.9 and R.sub.25. The emitter of the transistor Q.sub.9 of the reference voltage generation circuit 1 is connected to a terminal P.sub.13 and a negative third reference voltage V.sub.BB is obtained from this terminal P.sub.13.
The collector of the first input transistor Q.sub.18 and that of the reference transistor Q.sub.16 are connected to a first load resistor R.sub.32 at a first node N.sub.1 and the collector of the second input transistor Q.sub.17 is connected to a second load resistor R.sub.35 at a second node N.sub.2. When the first node N.sub.1 becomes high level, the first output transistor Q.sub.32 becomes conductive and an output signal of high level approximate to the positive power source voltage V.sub.CC is obtained at the output terminal P.sub.14. On the other hand, when the second node N.sub.2 becomes high level, the second output transistor Q.sub.33 becomes conductive and an output signal of low level approximate to the ground potential (GND) is produced at the output terminal P.sub.14. In this manner, the conversion output signal Y at the output terminal P.sub.14 of the signal level conversion circuit l.sub.2 varies substantially between the positive power source voltage V.sub.CC and the ground potential (GND) and is transmitted to the input terminal P.sub.15 of the TTL circuit l.sub.3.
By means of the connection arrangement outside the semiconductor integrated circuit, the output signal y of the ECL circuit l.sub.1 is applied to the first input terminal P.sub.11 of the signal level conversion circuit l.sub.2 while the third reference voltage V.sub.BB is applied to the second input terminal P.sub.12. In consequence, the phase of the conversion output signal Y at the output terminal P.sub.14 of the signal level conversion circuit l.sub.2 is opposite to the phase of the output signal y at the output terminal P.sub.7 of the ECL circuit l.sub.1.
Meanwhile, the negative power source voltage V.sub.EE for the first circuit such as the ECL circuit l.sub.1 and the positive power source voltage V.sub.CC for the second circuit such as the TTL circuit involve the possibility of inducing the fluctuation of the power source voltages, respectively.
Further, the switching speed of the output signal Y at the output terminal P.sub.14 of the signal level conversion circuit l.sub.2 is determined by the switching characteristics of the first and second input transistors Q.sub.18 and Q.sub.17.
In order to keep the switching speed of the signal level conversion circuit l.sub.2 at a high speed, therefore, the first and second input transistors Q.sub.18 and Q.sub.17 must be operated in the non-saturation mode. That is to say, when a bipolar transistor is driven into the saturation region, the base-collector junction is biased in the forward direction. Hence, the base layer and the collector layer cause minority carrier injection with each other and accumulation of this minority carrier markedly extends the switching time.
On the other hand, the reference voltage generation circuit 1 in the heretofore known signal level conversion circuit l.sub.2 shown in FIG. 1 generates a first reference voltage V.sub.b1 which depends upon the negative power source voltage V.sub.EE but not upon the positive power source voltage V.sub.CC, and by this first reference voltage V.sub.b1 is determined the value of a current I.sub.o flowing through the current source transistor Q.sub.19. Hence, the value of this current I.sub.o depends upon the value of the negative power source voltage V.sub.EE but not upon that of the positive power source voltage V.sub.CC.
Assume now that the output signal y at the output terminal P.sub.7 of the ECL circuit l.sub.1 is at a level which is approximate to the ground potential (GND). In this case, the second and third negative reference voltages V.sub.b2 and V.sub.BB are impressed upon the base of the reference transistor Q.sub.16 and upon that of the second input transistor Q.sub.17, respectively. Hence, the first input transistor Q.sub.18 becomes conductive while the reference transistor Q.sub.16 and the second input transistor Q.sub.17 remain non-conductive. Accordingly, the voltage V.sub.N1 at the first node N.sub.1 is given by the following equation; EQU V.sub.N1 =V.sub.CC -R.sub.32.I.sub.o ( 1)
When the negative power source voltage V.sub.EE is kept at a predetermined power source voltage (e.g., -5.2 V) while the positive power source voltage V.sub.CC drastically decreases from its predetermined power source voltage (e.g., +5.0 V) down to +3.0 V, for example, the first item on the right side of the above-mentioned equation (1) becomes smaller than the second item and hence, the voltage V.sub.N1 at the first node N.sub.1 becomes a negative voltage.
On the other hand, when the positive power source voltage V.sub.CC is kept at a predetermined power source voltage (e.g., 5.0 V) while the negative power source voltage V.sub.EE drastically increases from its predetermined power source voltage (e.g., -5.2 V) up to -7.0 V, for example, the value of the current I.sub.o flowing through the current source transistor Q.sub.19 increases. Due to the increase of the current, therefore, the second item of the equation (1) becomes greater than the first item. Thus, the voltage at the first node N.sub.1 becomes likewise a negative voltage.
Thus, the voltage V.sub.N1 at the first node N.sub.1 becomes a negative value due to the decrease of the positive power source voltage V.sub.CC or to the increase of the negative power source voltage V.sub.EE. At this time, since the output signal y, which is impressed upon the base of the first input transistor Q.sub.18, is at a level of the ground potential (GND), the collector-base junction of the first input transistor Q.sub.18 is biased in the forward direction and the first input transistor Q.sub.18 is driven into the saturation region.
On the other hand, when the third reference voltage V.sub.BB is impressed upon the base of the first input transistor Q.sub.18 and the output signal y of the ECL circuit l.sub.1 is impressed upon the base of the second input transistor Q.sub.17 in accordance with logic design of a data processing system, the voltage of the second node N.sub.2 becomes negative owing to the decrease of the positive power source voltage V.sub.CC or to the increase of the negative power source voltage V.sub.EE and the second input transistor Q.sub.17 is likewise driven into the saturation region.
In this manner, the saturation of the first input transistor Q.sub.18 or that of the second input transistor Q.sub.17, due to the fluctuation in the source voltage of the positive power source voltage V.sub.CC or the negative power source voltage V.sub.EE, markedly retards the switching speed of the output signal Y at the output terminal P.sub.14 of the signal level conversion circuit l.sub.2.
To cope with the problem, a method has conventionally been proposed which prevents the saturation of the input transistor by connecting a clamping element such as a Shottky barrier diode to the collector of the input transistors of the signal level conversion circuit, as disclosed in Japanese Patent Laid-Open No. 51-120143, for example.
Though the clamping element such as the Shottky barrier diode is capable of preventing the saturation of the input transistors, the switching speed of the output signal of the signal level conversion circuit is retarded due to the parasitic capacity inherent to the clamping element.
Referring again to the heretofore known signal level conversion circuit shown in FIG. 1, it has been clarified that when the absolute value .vertline.V.sub.EE .vertline. of the negative power source voltage -V.sub.EE becomes below about 4 V, the reference transistor Q.sub.16 as well as the current source transistor Q.sub.19 are brought into the OFF state. It has also been clarified that the collector outputs V.sub.N2, V.sub.N1 of the transistors Q.sub.17, Q.sub.18 are at high levels irrespective of the input conditions as represented by the power source voltage characteristic l.sub.71 in FIG. 7 whereby degradation of the characteristics of the output transistors Q.sub.32 and Q.sub.33 and their break-down occur.
This is because when the absolute value .vertline.V.sub.EE .vertline. of the negative power source voltage is not higher than about 4 V due to the base-emitter voltage of the transistor Q.sub.9, to the voltages of the diodes D.sub.3 and D.sub.4 in the forward direction, to the collector-base voltage of the current source transistor Q.sub.19 and to the voltage drop across the resistors R.sub.7 and R.sub.21, no current flows through them any longer.